CXMT Begins Fifth-Generation DRAM Production and Considers Strategic NAND Memory Expansion

The G5 platform is offered in 496-ball and 245-ball package configurations. It also uses a 45:1 array-capacitor aspect ratio, a DRAM-optimized high-k metal-gate process and new material integration to reduce the core-cell array height to 6,762 nanometers.
CXMT said it developed a digital-twin system covering the full product lifecycle—from design and development through manufacturing and maintenance—to shorten research-and-development cycles. The company also cited progress in interface engineering, saddle-fin structures and low-k spacer bitlines.
The reported NAND expansion initially lifted CXMT shares 3.4% to 55.29 yuan, underscoring the market’s reaction to the company’s potential move beyond DRAM into flash memory.
AI data-center investment has led major memory manufacturers to prioritize high-margin products such as high-bandwidth memory (HBM), while capital spending on DRAM and HBM has limited additions to NAND capacity. That shift has contributed to supply bottlenecks and rising prices for general-purpose DDR4 and DDR5 memory.
CXMT is positioning itself primarily as a high-volume, cost-effective supplier for mainstream consumer and server hardware, while Samsung, SK Hynix and Micron continue to lead in cutting-edge process nodes and advanced AI memory.
Chinese memory maker CXMT has begun mass production of its fifth-generation DRAM platform, introducing two 24Gb LPDDR5X chips that pack 50% more capacity than the previous generation Trendforce. The achievement marks a major step toward challenging Samsung, SK Hynix, and Micron in the global memory market, backed by an $8.6 billion IPO and a reported $3 billion supply deal with Tencent Reuters.
CXMT's G5 process uses self-aligned quadruple patterning to reach an 11.95-nanometer half-pitch while boosting output by at least 50% per wafer Trendforce. The company plans to ramp monthly production from roughly 300,000 wafers today to 375,000 by year-end 2026, capitalizing on AI-driven demand and persistent memory shortages expected through 2027 Reuters.
CXMT engineered the G5 to achieve significant miniaturization without relying on extreme ultraviolet (EUV) lithography, a technology restricted by US export controls TheRegister. The design cuts the core-cell array height to 6,762 nanometers and uses a 45:1 array-capacitor aspect ratio, along with high-k metal-gate processing and saddle-fin structures Pandaily. The 24Gb LPDDR5X chips come in 496-ball and 245-ball package options for smartphones and portable electronics.
To accelerate research cycles, CXMT built a digital-twin platform covering the entire product lifecycle—from design and manufacturing through maintenance Pandaily. The system simulates production processes and yield challenges before chips reach the fab, reducing costly trial-and-error cycles. CXMT also advanced interface engineering and low-k spacer bitline designs to optimize performance and power efficiency in the G5 platform.
CXMT is exploring a 3D NAND flash production line at a planned Beijing facility, a move that would pit it against China's Yangtze Memory Technologies and global NAND leaders Reuters. The company has held preliminary discussions with potential customers, including an AI-focused storage firm, though commercial-scale production remains years away. News of the plan lifted CXMT shares 3.4% to 55.29 yuan, signaling investor appetite for diversification beyond DRAM Reuters.
Samsung, SK Hynix, and Micron are pouring capital into high-bandwidth memory for AI data centers, leaving supply gaps in standard DDR4 and DDR5 for consumer and server hardware Reuters. CXMT is filling that void as a high-volume, cost-effective alternative. The company increased monthly wafer output from about 40,000 in 2020 to roughly 300,000 today, supported by its $8.6 billion IPO and the multi-year Tencent supply pact worth approximately $3 billion Reuters.
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