Chip Innovation Accelerates
CADFEM APAC and SilTerra Malaysia Partner to Drive Semiconductor Innovation with Digital Engineering
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CADFEM APAC and SilTerra Malaysia signed a Memorandum of Understanding on June 12, 2026, in Seberang Perai, Malaysia, to bring simulation-driven engineering into the heart of SilTerra's chip-making operations. PR Newswire reported that the deal aims to cut development risk and accelerate innovation at one of Malaysia's leading semiconductor foundries.
The partnership comes as Malaysia pushes hard to move beyond low-margin chip packaging. The country's National Semiconductor Strategy targets RM500 billion in investment and a major shift toward front-end chip design and fabrication, according to Yahoo Finance.
What DTCO and STCO Actually Mean for SilTerra
The core of the deal is building two frameworks called DTCO and STCO. DTCO stands for Design-Technology Co-Optimization — it means chip designers and factory engineers work together from day one, instead of in separate silos. STCO, or System-Technology Co-Optimization, goes a step further: it looks at how a chip performs inside a real device, like an EV motor or an AI server, not just on its own.
SilTerra Senior Vice President Beng Joo Thung said the goal is "connecting design, process development, and manufacturing within a unified engineering framework," according to PR Newswire. CADFEM provides the "digital twin" tools — software that simulates how heat, stress, and electricity affect a chip before a single wafer is ever made.
Agentic AI Could Autonomously Redesign Chip Processes
The partnership also includes plans to explore Agentic AI — a type of AI that doesn't just flag errors but actively runs simulations and optimizes chip designs on its own. This is different from standard AI tools. Instead of checking a designer's work, these AI agents could propose better manufacturing processes without being told exactly what to look for.
Industry observers describe this as a potential "leapfrog" move for a foundry that has historically focused on mature chip nodes between 110nm and 180nm. Critics, however, warn that Agentic AI remains largely unproven in real foundry environments. The hardest challenge, some researchers say, will be matching CADFEM's simulations to SilTerra's actual silicon yields on the factory floor.
SilTerra's Financial Pressure Makes This Deal Necessary
SilTerra's parent company, Dagang NeXchange Berhad (DNeX), posted a Loss Before Tax of RM28.9 million in mid-2025. DNeX total revenue for FY2024 reached RM1.2 billion, with SilTerra's technology segment contributing 54% of that, according to Yahoo Finance. A May 2025 power outage at Kulim Hi-Tech Park also forced temporary operational shutdowns, exposing infrastructure vulnerabilities.
For SilTerra, the CADFEM partnership is partly a cost-control play. Simulation tools can reduce expensive physical test runs. If successful, this shift could move SilTerra from a low-margin commodity foundry to a higher-margin specialty foundry — a critical step for a company competing against far larger players in Taiwan and South Korea.
Malaysia Bets Big on Chip Design to Escape the Assembly Trap
Malaysia currently holds about 13% of the global back-end semiconductor market — the lower-value work of packaging and testing chips made elsewhere. The government has committed RM25 billion in fiscal support to change that, targeting 60,000 newly trained engineers under the National Semiconductor Strategy launched in May 2024, according to Yahoo Finance.
By partnering with CADFEM, an Ansys-based simulation provider tied to US-headquartered Synopsys, SilTerra signals alignment with Western design standards. Analysts see this as a deliberate move. Malaysia is positioning itself as neutral ground in the US-China chip rivalry — able to supply global markets while staying compatible with American technology ecosystems.
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